Address Translation-1 MCQ’s

Computer Architecture Electronics & Communication Engineering

This set of Computer Architecture Multiple Choice Questions & Answers (MCQs) focuses on “Address Translation-1″.

1. The memory allocated to each page is contiguous.
a) True
b) False

2. The pages size shouldn’t be too small, as this would lead to __________
a) Transfer errors
b) Increase in operation time
c) Increase in access time
d) Decrease in performance

3. For converting a virtual address into the physical address, the programs are divided into __________
a) Pages
b) Frames
c) Segments
d) Blocks

4. The cache bridges the speed gap between ______ and __________
a) RAM and ROM
b) RAM and Secondary memory
c) Processor and RAM
d) None of the mentioned

5. The higher order bits of the virtual address generated by the processor forms the _______
a) Table number
b) Frame number
c) List number
d) Page number

6. The lower order bits of the virtual address forms the __________
a) Page number
b) Frame number
c) Block number
d) Offset

7. The virtual memory bridges the size and speed gap between __________ and __________
a) RAM and ROM
b) RAM and Secondary memory
c) Processor and RAM
d) None of the mentioned

8. The page length shouldn’t be too long because ___________
a) It reduces the program efficiency
b) It increases the access time
c) It leads to wastage of memory
d) None of the mentioned

9. The area in the main memory that can hold one page is called as ___________
a) Page entry
b) Page frame
c) Frame
d) Block

10. The starting address of the page table is stored in __________
a) TLB
b) R0
c) Page table base register
d) None of the mentioned

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