Fast Adders MCQ’s

Computer Architecture Electronics & Communication Engineering

This set of Computer Architecture Multiple Choice Questions & Answers (MCQs) focuses on “Fast Adders”.

1. The logic operations are implemented using _______ circuits.
a) Bridge
b) Logical
c) Combinatorial
d) Gate

2. The carry generation function: ci + 1 = yici + xici + xiyi, is implemented in ____________
a) Half adders
b) Full adders
c) Ripple adders
d) Fast adders

3. The logic operations are simpler to implement using logic circuits.
a) True
b) False

4. Which option is true regarding the carry in the ripple adders?
a) Are generated at the beginning only
b) Must travel through the configuration
c) Is generated at the end of each operation
d) None of the mentioned

5. The usual implementation of the carry circuit involves _________
a) And & or gates
b) XOR
c) NAND
d) XNOR

6. In a normal adder circuit, the delay obtained in a generation of the output is _______
a) 2n + 2
b) 2n
c) n + 2
d) None of the mentioned

7. In full adders the sum circuit is implemented using ________
a) And & or gates
b) NAND gate
c) XOR
d) XNOR

8. A _______ gate is used to detect the occurrence of an overflow.
a) NAND
b) XOR
c) XNOR
d) AND

9. The final addition sum of the numbers, 0110 & 0110 is ____________
a) 1101
b) 1111
c) 1001
d) 1010

10. The delay reduced to in the carry look ahead adder is __________
a) 5
b) 8
c) 10
d) 2n

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